An efficient algorithm for digital circuits testing /
With complex integrated circuits implemented either in FPGA or densley packed printed boards the testability problem arises. Since its inception in the mid eighties and its adoption by the IEEE organization as an international standard, boundary-scan technology has rapidly become the technology of c...
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| Format: | Book Chapter |
| Jezik: | English |
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4th World Multi-Conference on: Circuits, Systems, Communications and Computers, (CSCC 2000) [and] 2nd International Conference on: Mathematics and Computers in Physics (MCP 2000) [and] 2nd International Conference on: Mathematics and Computers in Mechanical Engineerings (MCME 2000) |
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| 008 | 030514s2000 xxu|||||s|||||||| ||eng c | ||
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| 041 | 0 | |a eng |b eng | |
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| 100 | 1 | |a Dugonik, Bogdan. |4 aut | |
| 245 | 0 | 0 | |a An efficient algorithm for digital circuits testing / |c Bogdan Dugonik. |
| 300 | |a 6 str. | ||
| 520 | |a With complex integrated circuits implemented either in FPGA or densley packed printed boards the testability problem arises. Since its inception in the mid eighties and its adoption by the IEEE organization as an international standard, boundary-scan technology has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. This Paper presents an efficient sequential circuit automatic test generation algorithm in conjunction with boundary scan technology. Software tools include Automatic boundary-scan Test Program Generator (ATPG) and boundary-scan Diagnostics. Most pattern generators employD-algorithm, Podem, Lasar or other known methods. The algorithm is basedon circuit simulation which has implemented a primitive error model to obtain a list of responses for each implemented failure. Test stimuli for automatic test equipment can be obtained either from test vectors written by circuit designers and/or diagnostics engineers, from an automatic test pattern generator (ATPG) or from some combination of these sources. The test response can be obtained either by simulating the test stimuli or by running the test stimuli on a reference board and monitoring response. We have studied an alternative method for creating an optimal test for testing digital combinational or sequentional circuits on single "stuck at" failures. The final result is a diagnostic and statistical file that enables us to obtain optimal test vectors for maximal fault coverage or for distinguish the detected faults in order to obtain better fault diagnostics. We designed a fault-detection experiment in an implemented FPGA design supported by boundary scan emulator. | ||
| 653 | 0 | |a testiranje |a obrobno pregledovanje |a generator vzorcev |a digitalna vezja |a zatične napake | |
| 653 | 0 | |a testing |a boundary scan |a pattern generator |a logical circuits |a stuck-at | |
| 773 | 0 | |a World Multi-Conference on: Circuits, Systems, Communications and Computers (4 : 2000 : Athens) |t 4th World Multi-Conference on: Circuits, Systems, Communications and Computers, (CSCC 2000) [and] 2nd International Conference on: Mathematics and Computers in Physics (MCP 2000) [and] 2nd International Conference on: Mathematics and Computers in Mechanical Engineerings (MCME 2000) |d [S.l.] : World Scientific : Engineering Society, 2000 |w 15309863 |z 960805219X |g 6 str. | |